API

Unified Chip Design Platform - SystemVerilog Support.

Modules:

Name	Description
svexprresolver	SystemVerilog Expression Resolver.
svimporter	SystemVerilog Importer.

Classes:

Name	Description
SvExprResolver	SystemVerilog Expression Resolver.

Functions:

Name	Description
get_resolver	Get SvExprResolver for mod.
import_params_ports	Import Parameter and Ports.

SvExprResolver

Bases: ExprResolver

SystemVerilog Expression Resolver.

This Expression Resolver Converts the UCDP internal expression representation into SystemVerilog.

Example

>>> import ucdp as u
>>> import ucdpsv as usv
>>> resolver = usv.SvExprResolver()
>>> resolver.resolve(u.ConstExpr(u.UintType(18, default=5)))
"18'h00005"
>>> resolver.resolve(u.ConstExpr(u.SintType(18, default=-5)))
"18'sh3FFFB"

Methods:

Name	Description
get_paramdecls	Return Align With Parameter Declarations.
get_localparamdecls	Return Align With Local Parameter Declarations.
get_portdecls	Return Align With Port Declarations.
get_signaldecls	Return Align With Signal Declarations.
get_instparams	Return Align With Parameter Declarations.
get_instcons	Return Align With Parameter Declarations.
get_defaults	Get Assigns.
get_assigns	Get Systemverilog Continuous Assigns.
get_decl	Get SV Declaration.
get_dims	Get SV Dimensions.
get_default	Get SV Default.
get_value	Get SV Value.
get_ident_expr	Get Ident Expression.
split_mux_conds	Split Multiplexer Conditions.

get_paramdecls

get_paramdecls(idents, is_last=True, indent=0)

Return Align With Parameter Declarations.

get_localparamdecls

get_localparamdecls(idents, indent=0)

Return Align With Local Parameter Declarations.

get_portdecls

get_portdecls(
    ports,
    is_last=True,
    indent=0,
    wirenames=None,
    no_comments=False,
)

Return Align With Port Declarations.

get_signaldecls

get_signaldecls(signals, indent=0, wirenames=None)

Return Align With Signal Declarations.

get_instparams

get_instparams(mod, is_last=True, indent=0)

Return Align With Parameter Declarations.

get_instcons

get_instcons(instcons, skips=None, is_last=True, indent=0)

Return Align With Parameter Declarations.

get_defaults

get_defaults(assigns, indent=0, oper='=')

Get Assigns.

get_assigns

get_assigns(assigns, indent, oper='')

Get Systemverilog Continuous Assigns.

get_decl

get_decl(type_)

Get SV Declaration.

get_dims

get_dims(type_)

Get SV Dimensions.

get_default

get_default(type_)

Get SV Default.

get_value

get_value(ident)

Get SV Value.

get_ident_expr

get_ident_expr(type_, name, op)

Get Ident Expression.

split_mux_conds

split_mux_conds(sel, conds)

Split Multiplexer Conditions.

get_resolver

get_resolver(mod, inst=None)

Get SvExprResolver for mod.

import_params_ports

import_params_ports(
    mod,
    filelistname="hdl",
    filepath=None,
    paramattrs=None,
    constattrs=None,
    portattrs=None,
)

Import Parameter and Ports.